1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to various methods of controlling gate electrode doping, and systems for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor is typically formed above a surface of a semiconducting substrate or wafer comprised of doped silicon. The substrate may be doped with either N-type or P-type dopant materials. The transistor typically has a doped polycrystalline silicon (polysilicon) gate electrode formed above a gate insulation layer comprised of, for example, silicon dioxide. The gate electrode and the gate insulation layer may be separated from doped source/drain regions of the transistor by a dielectric sidewall spacer. The source/drain regions of the transistor may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate. Shallow trench isolation regions may be provided to isolate the transistor electrically from neighboring semiconductor devices, such as other transistors.
In the process of forming integrated circuit devices, millions of transistors are formed above a semiconducting substrate. In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, metals, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes, along with various ion implant and heating processes, are continued until such time as the integrated circuit device is complete. Additionally, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
Moreover, there is a constant effort to increase the yield of the manufacturing processes used to form the integrated circuit devices. In turn, this involves manufacturing transistors, and the various components thereof, e.g., the gate insulation layer, the gate electrode, etc., in accordance with very precise design requirements. As device performance continues to be driven toward greater operating speeds, optimizing every facet of manufacturing integrated circuit devices is important to improve yields. This is even more important in the field of manufacturing integrated circuits where there is also great pressure to reduce manufacturing costs while delivering devices with the desired performance capabilities.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems described above.